1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory, more particularly, to a non-volatile semiconductor memory configured to perform a reading operation using the bit line shield technique.
2. Description of the Related Art
An electrically erasable programmable read-only memory (EEPROM) is known as a non-volatile semiconductor memory. Among EEPROMs, a NAND flash EEPROM having cell units in which a plurality of memory cells are connected to each other in series in a cell array is widely used.
In a NAND flash EEPROM, storage capacity has been increased in order to store a large quantity of data. For miniaturizing a memory cell while increasing the storage capacity, a parasitic capacitance between bit lines, which adjoin each other, is more common compared to a parasitic capacitance between a ground point and a bit line connected to a cell unit in a cell array. For example, when a bit line, which adjoins another bit line having a pre-charged potential, is electrically discharged in a reading operation, the pre-charged potential is decreased by the discharge of the adjoined bit line. Accordingly, a reading error may occur.
In order to prevent reading errors, in a NAND flash EEPROM, a “bit line shield technique” is proposed for solving this problem. In reading operations using the bit line shield technique, one end of a bit line, which is connected to a cell unit in a cell array, is connected via a bit line shield transistor to a shield power supply which supplies a potential for shielding the bit line. Alternatively, the other end of the bit line is connected via a bit line selection transistor to a sense amplifier, which latches a potential of the bit line.
In a NAND flash EEPROM using the bit line shield technique, the data of a group of memory cells (page) which are connected to a common word line are read out in two installments. For example, in a first reading operation, bit line shield transistors which are respectively connected to the odd bit lines are in a conducting state. The shield power supply supplies a ground potential to the odd bit lines, and thereby the odd bit lines are shielded. Simultaneously, the bit line selection transistors which are respectively connected to the even bit lines are in a conducting state, the data of the even bit lines is read out via the sense amplifier.
In a second reading operation, the bit line shield transistors which are respectively connected to the even bit lines are in a conducting state. The shield power supply supplies a ground potential to the even bit lines, and thereby the even bit lines are shielded. Simultaneously, the bit line selection transistors which are connected to the odd bit lines are in a conducting state, and data of the odd bit lines are read out via the sense amplifier.
However, an area of the bit line selection transistors which are connected to one end of the bit lines, and another area of the bit line shield transistors which are connected to the other end of the bit lines, are disposed at opposite sides of the cell array. For this reason, since an integration circuit of the area of the bit line selection transistors and the area of the bit line shield transistors is decreased, there is problem of increasing the circuit area.